HD6473228P10V Datasheet, PDF (64/301 Pages) Renesas Technology Corp – Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp

Interrupt
request
Exception -
handling state
Program
execution state
Exception
handling
Interrupt request
SLEEP instruction
with SSBY bit set
SLEEP
instruction
Sleep mode
RES = 1
Reset state
NMI or IRQ 0
to IRQ2 input
strobe interrupt
STBY=1 or RES=0
Software
standby mode
Hardware
standby mode
Power-down state
Notes:
1. A transition to the reset state occurs when RES goes Low, except when the chip is in the hardware standby mode.
2. A transition from any state to the hardware standby mode occurs when STBY goes Low.
Figure 3-12. State Transitions
3.6.1 Program Execution State
In this state the CPU executes program instructions in seq_Fu_ie_gn_. c₃e_-.₁₂The main program, subroutines,
and interrupt-handling routines are all executed in this state.
3.6.2 Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU is reset or accepts an
interrupt. In this state the CPU carries out a hardware-controlled sequence that prepares it to
execute a user-coded exception-handling routine.
In the hardware exception-handling sequence the CPU does the following:
(1) Saves the program counter and condition code register to the stack (except in the case of a
reset).
(2) Sets the interrupt mask (I) bit in the condition code register to “1.”
(3) Fetches the start address of the exception-handling routine from the vector table.
(4) Branches to that address, returning to the program execution state.
See section 4, “Exception Handling,” for further information on the exception-handling state.
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