HD6473228P10V Datasheet, PDF (185/301 Pages) Renesas Technology Corp – Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp

Bit 5 – Overrun Error (ORER): This bit indicates an overrun error during reception.
Bit 5
ORER
0
1
Description
To clear ORER, the CPU must read ORER after
it has been set to 1, then write a 0 in this bit.
This bit is set to 1 if reception of the next character ends while
the receive data register is still full (RDRF = 1).
(Initial value)
Bit 4 – Framing Error (FER): This bit indicates a framing error during data reception in asyn-
chronous mode. It has no meaning in synchronous mode.
Bit 4
FER
0
1
Description
To clear FER, the CPU must read FER after
it has been set to 1, then write a 0 in this bit.
This bit is set to 1 if a framing error occurs (stop bit = 0).
(Initial value)
Bit 3 – Parity Error (PER): This bit indicates a parity error during data reception in asynchro-
nous mode, when a communication format with parity bits is used.
This bit has no meaning in synchronous mode, or when a communication format without parity bits
is used.
Bit 3
PER
0
1
Description
To clear PER, the CPU must read PER after
it has been set to 1, then write a 0 in this bit.
This bit is set to 1 when a parity error occurs (the parity of the
received data does not match the parity selected by the O/E bit
in the SMR).
(Initial value)
Bits 2 to 0 – Reserved: These bits cannot be modified and are always read as 1.
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