HD6473228P10V Datasheet, PDF (204/301 Pages) Renesas Technology Corp – Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp

10.3 RAM Enable Bit (RAME)
The on-chip RAM is enabled or disabled by the RAME (RAM Enable) bit in the system control
register (SYSCR). Table 10-1 lists information about the system control register.
Table 10-1. System Control Register
Name
System control register
Abbreviation R/W
SYSCR
R/W
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
Initial value Address
H’0B
H’FFC4
3
2
1
0
— NMIEG — RAME
1
0
1
1
—
R/W
—
R/W
The only bit in the system control register that concerns the on-chip RAM is the RAME bit. See
section 2.4.2, System Control Register for the other bits.
Bit 0 – RAM Enable (RAME): This bit enables or disables the on-chip RAM.
The RAME bit is initialized to 1 on the rising edge of the RES signal, so a reset enables the on-chip
RAM. The RAME bit is not initialized in the software standby mode.
Bit 7
RAME
0
1
Description
On-chip RAM is disabled.
On-chip RAM is enabled.
(Initial value)
10.4 Operation
10.4.1 Expanded Modes (Modes 1 and 2)
If the RAME bit is set to 1, accesses to the following addresses are directed to the on-chip RAM.
H8/3257, H8/3256: H'F780 to H'FF7F
H8/325, H8/324: H'FB80 to H'FF7F
H8/323: H'FD80 to H'FF7F
H8/322: H'FE80 to H'FF7F
If the RAME bit is cleared to 0, accesses to these addresses are directed to the external data bus.
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