|
HD6473228P10V Datasheet, PDF (247/301 Pages) Renesas Technology Corp – Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp | |||
|
◁ |
Table 15-8. Timing Conditions of On-Chip Supporting Modules (cont.)
Condition A: VCC = 5.0V ±10%, à = 0.5 to 10MHz, VSS = 0V,
Ta = â20 to 75ËC (regular specifications), Ta = â40 to 85ËC (wide-range specifications)
Condition B: VCC = 2.7 to 3.6V, VSS = 0V, Ta = â20 to 75ËC, for only H8/3257 and H8/3256
Item
TMR
SCI
Ports
Condition B
Condition A
5MHz
6MHz
8MHz
10MHz
Symbol min max min max min max min max
Timer output tTMOD â
150 â
100 â
100 â
100
delay time
Timer reset
tTMRS 80 â
50 â
50 â
50 â
input setup time
Timer clock
tTMCS 80 â
50 â 50 â 50 â
input setup time
Timer clock
tTMCWH 1.5 â
1.5 â 1.5 â 1.5 â
pulse width
(single edge)
Timer clock
tTMCWL 2.5 â
2.5 â 2.5 â 2.5 â
pulse width
(both edges)
Input (Async) tScyc
2
â
2
â
2
â
2
â
clock (Sync) tScyc
4
â
4
â
4
â
4
â
cycle
Transmit data tTXD â
200 â
100 â
100 â
100
delay time (Sync)
Receive data
tRXS
150 â
100 â
100 â
100 â
setup time (Sync)
Receive data
tRXH 150 â
100 â
100 â
100 â
hold time (Sync)
Input clock
tSCKW 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6
pulse width
Output data
tPWD
â
150 â
100 â
100 â
100
delay time
Input data setup tPRS
80 â
50 â
50 â
50 â
time
Input data hold tPRH
80 â
50 â
50 â
50 â
time
Measurement
Unit conditions
ns Fig. 15-13
ns Fig. 15-15
ns Fig. 15-14
tcyc Fig. 15-14
tcyc Fig. 15-14
tcyc Fig. 15-16
tcyc Fig. 15-16
ns Fig. 15-16
ns Fig. 15-16
ns Fig. 15-16
tScyc Fig. 15-17
ns Fig. 15-18
ns Fig. 15-18
ns Fig. 15-18
244
|
▷ |