HD6473228P10V Datasheet, PDF (138/301 Pages) Renesas Technology Corp – Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp

Bit 2
OEA
0
1
Description
Output compare A output is disabled.
Output compare A output is enabled.
(Initial value)
Bits 1 and 0 – Clock Select (CKS1 and CKS0): These bits select external clock input or one of
three internal clock sources for the FRC. External clock pulses are counted on the rising edge.
Bit 1
CKS1
0
0
1
1
Bit 0
CKS0
0
1
0
1
Description
Ø/2 Internal clock source
Ø/8 Internal clock source
Ø/32 Internal clock source
External clock source (rising edge)
(Initial value)
7.2.5 Timer Control/Status Register (TCSR) – H’FF91
Bit
Initial value
Read/Write
7
ICF
0
R/(W)*
6
OCFB
0
R/(W)*
5
OCFA
0
R/(W)*
4
3
2
OVF OLVLB OLVLA
0
0
0
R/(W)* R/(W) R/(W)
1
IEDG
0
R/(W)
0
CCLRA
0
R/W
* Software can write a 0 in bits 7 to 4 to clear the flags, but cannot write a 1 in these bits.
The TCSR is an 8-bit readable and partially writable register that contains the four interrupt flags
and selects the output compare levels, input capture edge, and whether to clear the counter on
compare-match A.
The TCSR is initialized to H’00 at a reset and in the standby modes.
Bit 7 – Input Capture Flag (ICF): This status bit is set to 1 to flag an input capture event,
indicating that the FRC value has been copied to the ICR.
ICF must be cleared by software. It is set by hardware, however, and cannot be set by software.
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