HD6473228P10V Datasheet, PDF (129/301 Pages) Renesas Technology Corp – Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp

Port 3 write
Ø
Port 3
OS
Same data held
Same state held
T1
T2
Software
standby mode
Clock
settling time
T1 + T2 = 7 system clocks
Figure 6-5. Output Strobe Timing in Software Standby Mode
When the ISIE and LTE bits in the handshake control/status register (HCSR) are both set to 1, if a
high-to-low transition of the IS signal occurs during software standby mode, an input strobe
interrupt is requested and the chip recovers from software standby mode to handle the interrupt.
If the parallel handshaking interface is set for input, the port 3 input data are also latched.
If either the ISIE or LTE bit is cleared to 0, then high-to-low transitions of the IS signal are ignored
during software standby mode.
Fig 6-5
6.3.4 Sample Application
Figure 6-6 shows an example in which the parallel handshaking interface is used to interconnect
two H8/325 chips. Figure 6-7 shows the interface timing.
P3 7 to P30
OS
IS
H8/325 (sending chip)
P3 7 to P30
IS
OS
H8/325 (receiving chip)
Figure 6-6. Sample Usage of Parallel Handshaking Interface
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