H838776 Datasheet, PDF (469/594 Pages) Renesas Technology Corp – 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers

Section 21 Address Break
21.2 Operation
When the ABIF2 and ABIE2 bits in ABRKSR2 are set to 1, the address break function generates
an interrupt request to the CPU. The ABIF2 bit in ABRKSR2 is set to 1 by the combination of the
address set in BAR2, the data set in BDR2, and the conditions set in ABRKCR2. When the
interrupt request is accepted, interrupt exception handling starts after the instruction being
executed ends. The address break interrupt is not masked by the I bit in CCR of the CPU.
Figures 21.2 show the operation examples of the address break interrupt setting.
When the address break is specified in instruction execution cycle
Register setting
• ABRKCR2 = H'80
• BAR2 = H'025A
Program
0258 NOP
* 025A NOP
025C MOV.W @H'025A,R0
0260 NOP
0262 NOP
:
:
Underline indicates the address
to be stacked.
φ
Address
bus
Interrupt
request
NOP NOP MOV MOV
instruc- instruc- instruc- instruc-
tion
tion tion 1 tion 2 Internal
prefetch prefetch prefetch prefetch processing
Stack save
0258 025A 025C 025E
SP-2 SP-4
Interrupt acceptance
Figure 21.2 Address Break Interrupt Operation Example (1)
Rev. 1.00 Dec. 18, 2006 Page 447 of 568
REJ09B0348-0100