H838776 Datasheet, PDF (413/594 Pages) Renesas Technology Corp – 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers

Section 18 A/D Converter
18.3.3 A/D Start Register (ADSR)
ADSR starts and stops the A/D conversion.
Bit
7
6 to 0
Initial
Bit Name Value R/W
ADSF
0
R/W

All 1 
Description
When this bit is set to 1, A/D conversion is started.
When conversion is completed, the converted data is
set in ADRR and at the same time this bit is cleared to
0. If this bit is written to 0, A/D conversion can be
forcibly terminated.
Reserved
These bits are always read as 1 and cannot be
modified.
18.4 Operation
The A/D converter operates by successive approximation with 10-bit resolution. When changing
the conversion time or analog input channel, in order to prevent incorrect operation, first clear the
bit ADSF to 0 in ADSR.
18.4.1 A/D Conversion
1. A/D conversion is started from the selected channel when the ADSF bit in ADSR is set to 1,
according to software.
2. When A/D conversion is completed, the result is transferred to the A/D result register.
3. On completion of conversion, the IRRAD flag in IRR2 is set to 1. If the IENAD bit in IENR2
is set to 1 at this time, an A/D conversion end interrupt request is generated.
4. The ADSF bit remains set to 1 during A/D conversion. When A/D conversion ends, the
ADSF bit is automatically cleared to 0 and the A/D converter enters the wait state.
Rev. 1.00 Dec. 18, 2006 Page 391 of 568
REJ09B0348-0100