H838776 Datasheet, PDF (329/594 Pages) Renesas Technology Corp – 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers

Section 15 Serial Communication Interface 3 (SCI3, IrDA)
Figure 15.1 (1) shows a block diagram of the SCI3_1 and figure 15.1 (2) shows that of the
SCI3_2.
TXD31
RXD31
SCK31
External clock
Baud rate generator
Internal clock (φ/64, φ/16, φw/2, φ)
Clock
BRC3_1
BRR3_1
Transmit/receive
control circuit
SMR3_1
SCR3_1
SSR3_1
TSR3_1
TDR3_1
SPCR
IrCR
RSR3_1
RDR3_1
Interrupt request
(TEI31, TXI31, RXI31, ERI31)
[Legend]
RSR3_1:Receive shift register 3_1
RDR3_1:Receive data register 3_1
TSR3_1: Transmit shift register 3_1
TDR3_1: Transmit data register 3_1
SMR3_1:Serial mode register 3_1
SCR3_1:Serial control register 3_1
SSR3_1: Serial status register 3_1
BRR3_1:Bit rate register 3_1
BRC3_1:Bit rate counter 3_1
SPCR: Serial port control register
IrCR: IrDA control register
Figure 15.1 (1) Block Diagram of SCI3_1
Rev. 1.00 Dec. 18, 2006 Page 307 of 568
REJ09B0348-0100