H838776 Datasheet, PDF (25/594 Pages) Renesas Technology Corp – 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers

Section 1 Overview
Module/
Classification Function Description
Clock
Clock pulse •
generator _•
(CPG)
Two clock generation circuits available
Separate clock signals are provided for each of functional
modules
• Includes frequency division circuit, so the operating frequency
is selectable
A/D converter
Timer
•
A/D
•
converter _•
(ADC)
•
•
14-bit PWM •
•
•
Realtime •
clock (RTC) _•
•
Timer F •
•
•
•
•
16-bit timer •
pulse unit _•
(TPU)
•
•
•
•
Seven low-power-consumption modes: Active (medium speed)
mode, Sleep (high speed or medium speed) mode, subactive
mode, subsleep mode, standby mode, and watch mode
10-bit resolution × eight input channels
Sample and hold function included
Conversion time: 12.4 µs per channel (with φ at 5-MHz
operation)
Two ways to start A/D conversion: software and external trigger
Two channels
Four conversion periods selectable
Pulse division method for ripple reduction
8-bit timer
Timer-base functionality: Seven interrupt periods (0.25 second
to one week) are selectable
Free running counter: Eight clock sources are selectable
16-bit timer (also can be used as two independent 8-bit timers)
Five counter input clocks
Output compare function supported
Toggle output function supported
two interrupt sources: Compare match and overflow
16 bits × two channels
Counter-input clocks selectable for each channel
Up to four pulse inputs and outputs
Waveform output by compare match, input capture function,
counter clear operation, simultaneous writing to and clearing of
multiple timer counters by compare match and input capture
possible, simultaneous input/output for registers possible by
counter synchronous operation, PWM output with a desired
duty cycle, and up to two-phase PWM output possible by
combination with synchronous operation
Cascaded operation
Six interrupt sources
Rev. 1.00 Dec. 18, 2006 Page 3 of 568
REJ09B0348-0100