H838776 Datasheet, PDF (10/594 Pages) Renesas Technology Corp – 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers

3.2.1 Reset Exception Handling .................................................................................. 57
3.2.2 Interrupt Immediately after Reset ....................................................................... 58
3.3 Interrupts............................................................................................................................. 59
3.4 Stack Status after Exception Handling ............................................................................... 60
3.4.1 Interrupt Response Time..................................................................................... 61
3.5 Usage Notes ........................................................................................................................ 62
3.5.1 Notes on Stack Area Use .................................................................................... 62
3.5.2 Notes on Rewriting Port Mode Registers ........................................................... 63
3.5.3 Method for Clearing Interrupt Request Flags ..................................................... 66
Section 4 Interrupt Controller.............................................................................. 67
4.1 Features............................................................................................................................... 67
4.2 Input/Output Pins................................................................................................................ 68
4.3 Register Descriptions.......................................................................................................... 68
4.3.1 Interrupt Edge Select Register (IEGR) ............................................................... 69
4.3.2 Wakeup Edge Select Register (WEGR).............................................................. 70
4.3.3 Interrupt Enable Register 1 (IENR1) .................................................................. 71
4.3.4 Interrupt Enable Register 2 (IENR2) .................................................................. 72
4.3.5 Interrupt Request Register 1 (IRR1) ................................................................... 73
4.3.6 Interrupt Request Register 2 (IRR2) ................................................................... 74
4.3.7 Wakeup Interrupt Request Register (IWPR) ...................................................... 76
4.3.8 Interrupt Priority Registers A to E (IPRA to IPRE)............................................ 78
4.3.9 Interrupt Mask Register (INTM) ........................................................................ 79
4.4 Interrupt Sources................................................................................................................. 79
4.4.1 External Interrupts .............................................................................................. 79
4.4.2 Internal Interrupts ............................................................................................... 81
4.5 Interrupt Exception Handling Vector Table........................................................................ 81
4.6 Operation ............................................................................................................................ 84
4.6.1 Interrupt Exception Handling Sequence ............................................................. 86
4.6.2 Interrupt Response Times ................................................................................... 88
4.7 Usage Notes ........................................................................................................................ 89
4.7.1 Contention between Interrupt Generation and Disabling.................................... 89
4.7.2 Instructions that Disable Interrupts..................................................................... 90
4.7.3 Interrupts during Execution of EEPMOV Instruction ........................................ 90
4.7.4 IENR Clearing .................................................................................................... 90
Section 5 Clock Pulse Generators ....................................................................... 91
5.1 Register Description ........................................................................................................... 93
5.1.1 SUB32k Control Register (SUB32CR)............................................................... 93
5.1.2 Oscillator Control Register (OSCCR) ................................................................ 94
Rev. 1.00 Dec. 18, 2006 Page x of xxii