H838776 Datasheet, PDF (314/594 Pages) Renesas Technology Corp – 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers

Section 13 Asynchronous Event Counter (AEC)
13.6 Usage Notes
1. When reading the values in ECH and ECL, first clear bits CUEH and CUEL to 0 in ECCSR in
8-bit mode and clear bit CUEL to 0 in 16-bit mode to prevent asynchronous event input to the
counter. The correct value will not be returned if the event counter increments while being
read.
2. For input to the AEVH and AEVL pins, use a clock with a frequency of up to 4.2 MHz within
the range from 1.8 to 3.6 V and up to 10 MHz within the range from 2.7 to 3.6 V. For the high
and low widths of the clock, see section 23, Electrical Characteristics. The duty cycle is
arbitrary.
Table 13.4 shows a maximum clock frequency.
Table 13.4 Maximum Clock Frequency
Mode
Active (high-speed), sleep (high-speed)
Active (medium-speed), sleep (medium-speed)
f = 1 MHz to 4 MHz
OSC
Watch, subactive, subsleep, standby
φ = 32.768 kHz or 38.4 kHz
W
Maximum Clock Frequency
Input to AEVH/AEVL Pin
10 MHz
(φ /8)
OSC
(φ_OSC/16)
(φ /32)
OSC
(φ /64)
OSC
(φ_W/2)
(φ /4)
W
(φ /8)
W
2·f
OSC
f_OSC
1/2 · f
OSC
1/4 · f
OSC
1000 kHz
500 kHz
250 kHz
3. When AEC uses with 16-bit mode, set CUEH in ECCSR to 1 first, set CRCH in ECCSR to 1
second, or set both CUEH and CRCH to 1 at same time before clock input. When AEC is
operating on 16-bit mode, do not change CUEH. Otherwise, ECH will be miscounted up.
4. When ECPWME in AEGSR is 1, the event counter PWM is operating and therefore ECPWCR
and ECPWDR should not be modified.
When changing the data, clear the ECPWME bit in AEGSR to 0 (halt the event counter PWM)
before modifying these registers.
5. The event counter PWM data register and event counter PWM compare register must be set so
that event counter PWM data register < event counter PWM compare register. If the settings
do not satisfy this condition, do not set ECPWME to 1 in AEGSR.
6. As synchronization is established internally when an IRQAEC interrupt is generated, a
maximum error of 1 tcyc will occur between clock halting and interrupt acceptance.
Rev. 1.00 Dec. 18, 2006 Page 292 of 568
REJ09B0348-0100