H838776 Datasheet, PDF (116/594 Pages) Renesas Technology Corp – 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers

Section 5 Clock Pulse Generators
5.1.2 Oscillator Control Register (OSCCR)
OSCCR contains flags indicating whether the system clock oscillator or on-chip oscillator is
selected and the input level on the IRQAEC pin during resets; the former flag bit also controls
whether the on-chip oscillator operates or not.
Initial
Bit
Bit Name Value R/W Description
7 to 3 —
All 0 R/W Reserved
These bits are readable/writable enable reserves bits.
2
IRQAECF —
R
IRQAEC flag
This bit indicates the IRQAEC pin input level set during
resets.
0: IRQAEC pin set to GND during resets
1: IRQAEC pin set to Vcc during resets
1
OSCF
—
R
OSC flag
This bit indicates the oscillator operating with the
system clock pulse generator.
0: System clock oscillator operating (on-chip oscillator
stopped)
1: On-chip oscillator operating (system clock oscillator
stopped)
0
—
0
R/W Reserved
Never write 1 to this bit, as it can cause the LSI to
malfunction.
Rev. 1.00 Dec. 18, 2006 Page 94 of 568
REJ09B0348-0100