7480 Datasheet, PDF (41/98 Pages) Bi technologies – 7/8 Diameter 5-Turn Wirewound Precision Potentiometer

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MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
STP/WIT Instruction Control
The STP instruction and the WIT instruction can be enabled or
disabled selectively by using the STP instruction operation control
register. To cope with a program runaway after reset, the STP in-
struction and the WIT instruction are disabled in the initial status.
The STP and WIT instructions can be set as enable/disable only
by writing to the STP instruction operation control register twice
successively so as not to stop the oscillation clock even if a write
data error is caused by program runaway. Figure 41 shows a
structure of the STP instruction operation control register.
b7
b0
STP instruction operation control register
(STPCON: address 00DE 16)
STP instruction and WIT instruction enable/disable selection bit (Note)
0 : STP/WIT instruction enabled
1 : STP/WIT instruction disabled
Not used (“0” at read)
Note : The STP instruction and the WIT instruction are disabled in the initial status. When using these
instructions, set bit 0 of the STP instruction operation control register to “1”, then set this bit to “0”.
(Writing twice successively)
When not using the STP and WIT instructions, set this bit to “1” either once or twice.
Fig. 41 Structure of STP instruction operation control register
Explanation of STP Instruction Operation
Control Register
The STP instruction operation control register will be enabled by
writing data to the same address twice successively. If data is not
written in continuous form, the written data is not valid but the pre-
vious value is held.
If an interrupt is received while the same data is written twice,
there is a possibility that the write instruction in the interrupt rou-
tine may be executed. For this reason, rewriting is required after
interrupt disable. Figure 42 shows a reference example of data re-
writing.
qSTP/WIT instruction enable
•
•
•
SEI
LDM #01H, 0DEH
LDM #00H, 0DEH
CLI
Interrupt
disable in
this period
•
•
• _{Use only in interrupt enable status}
Fig. 42 Reference example of data rewriting
qSTP/WIT instruction disable
•
•
•
SEI
LDM #01H, 0DEH
LDM #01H, 0DEH
CLI
Interrupt
disable in
this period
•
•
•
Use only in interrupt enable status
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