7480 Datasheet, PDF (34/98 Pages) Bi technologies – 7/8 Diameter 5-Turn Wirewound Precision Potentiometer

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MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Serial I/O Control Register] SIOCON
The serial I/O control register consists of 8 control bits for control
of the serial I/O.
[UART Control Register] UARTCON
The UART control register is a 4-bit control register which is valid
when UART is selected. This 4-bit control register sets a data for-
mat for serial data transfer.
[Serial I/O Status Register] SIOSTS
This is a 7-bit read-only register consisting of flags that indicate
the serial I/O operating status and different error flags. The 3 bits
of bit 4 to bit 6 are valid only in the UART mode.
The receive buffer full flag is cleared to “0” when the receive buffer
register is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set.
Writing to the serial I/O status register clears all the error flags
(OE, PE, FE, SE).
All the bits of this register are initialized to “0” at reset.
However, if the transmit enable bit of the serial I/O control register
is set to “1”, bit 2 and bit 0 become “1”.
[Transmit Buffer Register/Receive Buffer Register] TB/RG
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer register is a
write-only type and the receive buffer register is a read-only type.
If a character bit length is 7 bits, the MSB of the receive data
stored in the receive buffer is “0”.
[Baud Rate Generator] BRG
The baud rate generator determines a baud rate for serial transfer.
The baud rate generator, being an 8-bit counter with a reload reg-
ister, divides the frequency of the count source by 1/(n+1), where
n is the value written to the baud rate generator.
b7
b0 _{Serial I/O status register SIOSTS}
(address 00E116)
Transmit buffer empty flag (TBE)
0 : Buffer full
1 : Buffer empty
Receive buffer full flag (RBF)
0 : Buffer empty
1 : Buffer full
Transmit shift register shift completion flag (TSC)
0 : Transmit shift in progress
1 : Transmit shift completed
Overrun error flag (OE)
0 : No error
1 : Overrun error
Parity error flag (PE)
0 : No error
1 : Parity error
Framing error flag (FE)
0 : No error
1 : Framing error
Summing error flag (SE)
0 : (OE)U(PE)U(FE)=0
1 : (OE)U(PE)U(FE)=1
Not used (“1” at read)
b7
b0 _{Serial I/O control register SIOCON}
(address 00E216)
BRG count source selection bit (CSS)
0 : f(XIN)/4
1 : f(XIN)/16
Serial I/O synchronous clock selection bit (SCS)
0 : BRG output/4 (when clock synchronous
serial I/O is selected)
BRG output/16 (when UART is selected)
1 : External clock input (when clock synchronous
serial I/O is selected)
External clock input/16 (when UART is selected)
SRDY output enable bit (SRDY)
0 : P17 pin operates as ordinary I/O pin.
1 : P17 pin operates as SRDY output pin.
Transmit interrupt source selection bit (TIC)
0 : Interrupt when transmit buffer is empty.
1 : Interrupt when transmit shift operation is completed.
Transmit enable bit (TE)
0 : Transmit disabled
1 : Transmit enabled
Receive enable bit (RE)
0 : Receive disabled
1 : Receive enabled
Serial I/O mode selection bit (SIOM)
0 : Asynchronous serial I/O (UART)
1 : Clock synchronous serial I/O
Serial I/O enable bit (SIOE)
0 : Serial I/O disabled (P14 to P17: ordinary
I/O ports)
1 : Serial I/O enabled (P14 to P17: serial
I/O function pins)
b7
b0 _{UART control register UARTCON}
(address 00E316)
Character length selection bit (CHAS)
0 : 8-bit
1 : 7-bit
Parity enable bit (PARE)
0 : Parity disabled
1 : Parity enabled
Parity selection bit (PARS)
0 : Even parity
1 : Odd parity
Stop bit length selection bit (STPS)
0 : 1 stop bit
1 : 2 stop bits
Not used (“1” at read)
Fig. 32 Structure of serial I/O related registers (SIOSTS,
UARTCON, SIOCON)
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