7480 Datasheet, PDF (36/98 Pages) Bi technologies – 7/8 Diameter 5-Turn Wirewound Precision Potentiometer

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MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Bus Collision Detection
The 7480/7481 group can detect a bus collision by setting the bus
collision detection enable bit to “1”.
When transmission is started in the clock synchronous or asyn-
chronous (UART) serial I/O mode, the transmit pin TxD is
compared with the receive pin RxD in synchronization with a rising
edge of transmit shift clock. If they do not coincide with each other,
a bus arbitration interrupt request occurs (bus collision detection).
A transmit data collision is detected between LSB and MSB of
transmit data in the clock synchronous serial I/O mode or between
the start bit and stop bit of transmit data in the UART mode. Bus
collision detection can be performed by both the internal clock and
the external clock.
A block diagram is shown in Figure 34. A timing diagram is shown
in Figure 35. A bus collision detection control register is shown in
Figure 36.
TXD
RXD
Shift clock
Bus collision detection
enable bit
TE
Fig. 34 Block diagram of bus arbitration interrupt circuit
D
Q
Bus arbitration interrupt
request
Transmit shift clock
Transmit pin TxD
Receive pin RxD
Fig. 35 Timing diagram of bus arbitration interrupt
Bus arbitration interrupt
generation
Data collision
b7
b0
Bus collision detection control register
(BUSARBCON address 00E5 16)
Fig. 36 Structure of bus collision detection control register
Bus collision detection enable bit
0 : Collision detection disabled
1 : Collision detection enabled
Not used (“0” at read)
35