7480 Datasheet, PDF (19/98 Pages) Bi technologies – 7/8 Diameter 5-Turn Wirewound Precision Potentiometer

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MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 4. Interrupt vector addresses and priority
Interrupt source
RESET (Note 2)
INT0
INT1
Key-on wake-up
CNTR0
CNTR1
Timer X
Timer Y
Timer 1
Timer 2
Serial I/O reception
Serial I/O transmission
Bus arbitration
A-D conversion
Prior-
ity
1
2
3
4
5
6
7
8
9
10
11
12
13
Vector address (Note 1)
High-order Low-order
Interrupt request generating conditions
FFFF16 FFFE16 At reset
FFFD16
FFFC16
At detection of either rising edge or falling
edge of INT0 input
FFFB16
FFFA16
At detection of either rising edge or falling
edge of INT1 input
At input “L” to port P0 in key-on wake-up
mode
FFF916
FFF816
At detection of either rising edge or falling
edge of CNTR0 input
FFF716
FFF616
At detection of either rising edge or falling
edge of CNTR1 input
FFF516 FFF416 At timer X underflow
FFF316 FFF216 At timer Y underflow
FFF116 FFF016 At timer 1 underflow
FFEF16 FFEE16 At timer 2 underflow
FFED16 FFEC16 At completion of serial I/O data reception
FFEB16
FFEA16
At completion of serial I/O transfer shift or
when transmission buffer is empty
FFE916 FFE816 At detection of bus collision
FFE716 FFE616 At completion of A-D conversion
BRK instruction
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FFE516 FFE416 At execution of BRK instruction
Notes 1 : Vector addresses contain interrupt jump destination addresses.
2 : RESET is mentioned in the table because its operation is the same as an interrupt.
Remarks
Non-maskable
External interrupt
(active edge programmable)
External interrupt
(active edge programmable)
Validity after execution of
STP/WIT instruction
External interrupt
(active edge programmable)
External interrupt
(active edge programmable)
Non-maskable software
interrupt
Interrupt request bit
Interrupt enable bit
Interrupt disable flag
BRK instruction
Reset
Fig. 15 Interrupt control diagram
Interrupt request
18