7480 Datasheet, PDF (20/98 Pages) Bi technologies – 7/8 Diameter 5-Turn Wirewound Precision Potentiometer

PRELIMINARY _{NSootimcee: pTahriasmisentroict} ^{alimfinitsalasrpeescuifbicjeactitotno. change.}
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Edge polarity selection register (EG : address 00D4 16)
INT0 selection bit
0 : Falling edge
1 : Rising edge
INT1 selection bit
0 : Falling edge
1 : Rising edge
CNTR0 edge selection bit
0 : In event count mode, count rising edge.
: In pulse output mode, start at “H” level output.
: In pulse cycle measurement mode, measure a period from falling edge to falling edge.
: In pulse width measurement mode, measure an “H” period.
: In programmable one-shot output mode, generate one-shot “H” pulse after start at “L” output.
: Interrupt, falling edge active.
1 : In event count mode, count falling edge.
: In pulse output mode, start at “L” level output.
: In pulse cycle measurement mode, measure a period from rising edge to rising edge.
: In pulse width measurement mode, measure an “L” period.
: In programmable one-shot output mode, generate one-shot “L” pulse after start at “H” level output.
: Interrupt, rising edge active.
CNTR1 edge selection bit
0 : In event count mode, count rising edge.
: In pulse output mode, start at “H” level output.
: In pulse cycle measurement mode, measure a period from falling edge to falling edge.
: In pulse width measurement mode, measure an “H” period.
: In programmable one-shot output mode, generate one-shot “H” pulse after start at “L” level output.
: Interrupt, falling edge active.
1 : In event count mode, count falling edge.
: In pulse output mode, start at “L” output.
: In pulse cycle measurement mode, measure a period from rising edge to rising edge.
: In pulse width measurement mode, measure an “L” period.
: In programmable one-shot output mode, generate one-shot “L” pulse after start at “H” output.
: Interrupt rising edge active.
Not used (undefined at read)
INT1 source selection bit at STP or WIT
0 : P31/INT1
1 : P00 – P07 “L” level (for key-on wake-up)
Not used (undefined at read)
b7
b0
b7
b0
Interrupt control register 1 (ICON1: address 00FE 16)
Interrupt request register 1 (IREQ1: address 00FC16)
Timer X interrupt enable bit
Timer X interrupt request bit
Timer Y interrupt enable bit
Timer 1 interrupt enable bit
Timer Y interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt enable bit
Serial I/O receive interrupt enable bit
Timer 2 interrupt request bit
Serial I/O receive interrupt request bit
Serial I/O transmit interrupt enable bit
Serial I/O transmit interrupt request bit
Bus arbitration interrupt enable bit
A-D conversion completion interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Bus arbitration interrupt request bit
A-D conversion completion interrupt request bit
0 : No interrupt request
1 : Interrupt requested
b7
b0
b7
b0
Interrupt control register 2 (ICON2: address 00FF16)
Interrupt request register 2 (IREQ2: address 00FD16)
INT0 interrupt enable bit
INT1 interrupt enable bit
CNTR0 interrupt enable bit
CNTR1 interrupt enable bit
0 : Interrupt disable
1 : Interrupt enable
Not used (undefined at read)
0 : Interrupt disabled
1 : Interrupt enabled
INT0 interrupt request bit
INT1 interrupt request bit
CNTR0 interrupt request bit
CNTR1 interrupt request bit
0 : No interrupt request
1 : Interrupt request
Not used (undefined at read)
0 : No interrupt request
1 : Interrupt requested
Fig. 16 Structure of registers related to interrupts
19