|
HD6473258P10V Datasheet, PDF (38/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer | |||
|
◁ |
Unused area
SP
(R7)
Stack area
Figure 3-2. Stack Pointer
3.2.2 Control Registers
The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code
register (CCR).
(1) Program Counter (PC): This 16-bit register indicates the address of the next instruction the
CPU will execute. Each instruction is accessed in 16 bits (1 word), so the least significant bit of the
PC is ignored (always regarded as 0).
(2) Condition Code Register (CCR): This 8-bit register contains internal status information,
including carry (C), overflow (V), zero (Z), negative (N), and half-carry (H) flags and the interrupt
mask bit (I).
Bit 7âInterrupt Mask Bit (I): When this bit is set to â1,â all interrupts except NMI are masked.
This bit is set to â1â automatically by a reset and at the start of interrupt handling.
Bit 6âUser Bit (U): This bit can be written and read by software for its own purposes.
Bit 5âHalf-Carry (H): This bit is set to â1â when the ADD.B, ADDX.B, SUB.B, SUBX.B,
NEG.B, or CMP.B instruction causes a carry or borrow out of bit 3, and is cleared to â0â otherwise.
Similarly, it is set to â1â when the ADD.W, SUB.W, or CMP.W instruction causes a carry or borrow
out of bit 11, and cleared to â0â otherwise. It is used implicitly in the DAA and DAS instructions.
Bit 4âUser Bit (U): This bit can be written and read by software for its own purposes.
Bit 3âNegative (N): This bit indicates the most significant bit (sign bit) of the result of an
instruction.
29
|
▷ |