HD6473258P10V Datasheet, PDF (224/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

12.2 System Control Register: Power-Down Control Bits
Bits 7 to 4 of the system control register (SYSCR) concern the power-down state. Specifically,
they concern the software standby mode.
Table 12-2 lists the attributes of the system control register.
Table 12-2. System Control Register
Name
System control register
Abbreviation R/W
SYSCR
R/W
Initial value Address
H’0B
H’FFC4
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
2
1
0
— NMIEG — RAME
1
0
1
1
—
R/W
—
R/W
Bit 7 – Software Standby (SSBY): This bit enables or disables the transition to the software
standby mode.
On recovery from the software standby mode by an external interrupt or input strobe interrupt,
SSBY remains set to 1. To clear this bit, software must write a 0.
Bit 7
SSBY
0
1
Description
The SLEEP instruction causes a transition to the sleep mode.
The SLEEP instruction causes a transition to the software
standby mode.
(Initial value)
Bits 6 to 4 – Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the clock settling
time when the chip recovers from the software standby mode by an external interrupt. During the
selected time, the clock oscillator runs but clock pulses are not supplied to the CPU or the on-chip
supporting modules.
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