HD6473258P10V Datasheet, PDF (139/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Bit 7
ICF
0
1
Description
To clear ICF, the CPU must read ICF after it
has been set to 1, then write a 0 in this bit.
This bit is set to 1 when an FTI input signal causes the FRC
value to be copied to the ICR.
(Initial value)
Bit 6 – Output Compare Flag B (OCFB): This status flag is set to 1 when the FRC value matches
the OCRB value.
This flag must be cleared by software. It is set by hardware, however, and cannot be set by
software.
Bit 6
OCFB
0
1
Description
To clear OCFB, the CPU must read OCFB after
it has been set to 1, then write a 0 in this bit.
This bit is set to 1 when FRC = OCRB.
(Initial value)
Bit 5 – Output Compare Flag A (OCFA): This status flag is set to 1 when the FRC value matches
the OCRA value.
This flag must be cleared by software. It is set by hardware, however, and cannot be set by
software.
Bit 5
OCFA
0
1
Description
To clear OCFA, the CPU must read OCFA after
it has been set to 1, then write a 0 in this bit.
This bit is set to 1 when FRC = OCRA.
(Initial value)
Bit 4 – Timer Overflow Flag (OVF): This status flag is set to 1 when the FRC overflows (changes
from H’FFFF to H’0000).
This flag must be cleared by software. It is set by hardware, however, and cannot be set by
software.
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