HD6473258P10V Datasheet, PDF (141/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

7.2.6 FRT Noise Canceler Control Register (FNCR) – H’FFFF
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
— NCS1 NCS0
Initial value
1
1
1
1
1
1
0
0
Read/Write
—
—
—
—
—
— R/W R/W
The FNCR is an 8-bit readable/writable register that controls the input capture noise canceler.
The FNCR is initialized to H’FC at a reset and in the standby modes.
Bits 7 to 2 – Reserved: These bits cannot be modified, and are always read as 1.
Bits 1 and 0 – Noise Canceler Select 1 and 0 (NCS1 and NCS0): Select the sampling clock
provided to the noise canceler. Three internal clock rates can be selected.
The noise canceler recognizes a level change only if it is observed in four consecutive samples.
When the noise canceler is enabled, the input capture pulse width must be at least four sampling
clock cycles. See section 7.6, Noise Canceler for further information.
The noise canceler can be disabled by clearing both NCS1 and NCS0 to 0. The input capture pulse
width must then be at least 1.5 system clock cycles (1.5^.Ø) to assure capture.
Bit 1
NCS1
0
0
1
1
Bit 0
NCS0
0
1
0
1
Description
Noise canceler is disabled.
Sampling clock frequency: Ø/32
Sampling clock frequency: Ø/64
Sampling clock frequency: Ø/128
(Initial value)
7.3 CPU Interface
The free-running counter (FRC), output compare registers (OCRA and OCRB), and input capture
register (ICR) are 16-bit registers, but they are connected to an 8-bit data bus. When the CPU
accesses these registers, to ensure that both bytes are written or read simultaneously, the access is
performed using an 8-bit temporary register (TEMP).
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