HD6473258P10V Datasheet, PDF (231/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Section 13. E-Clock Interface
13.1 Overview
For interfacing to peripheral devices that require it, the H8/325 series can generate an E clock
output. Special instructions (MOVTPE, MOVFPE) perform data transfers synchronized with the E
clock.
The E clock is created by dividing the system clock (Ø) by 8. The E clock is output at the P47 pin
when the P47DDR bit in the port 4 data direction register (P4DDR) is set to 1. It is output only in
the expanded modes (mode 1 and mode 2); it is not output in the single-chip mode. Output begins
immediately after a reset.
When the CPU executes an instruction that synchronizes with the E clock, the address strobe (AS),
the address on the address bus, and the IOS signal are output as usual, but the RD and WR signal
lines and the data bus do not become active until the falling edge of the E clock is detected. The
length of the access cycle for an instruction synchronized with the E clock accordingly varies from
9 to 16 states. Figures 15-1 and 15-2 show the timing in the cases of maximum and minimum
synchronization delay.
It is not possible to insert wait states (Tw) during the execution of an instruction synchronized with
the E clock by input at the WAIT pin.
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