4570 Datasheet, PDF (32/69 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
RAM BACK-UP MODE
The 4570 Group has the RAM back-up mode.
When the EPOF and POF instructions are executed continuously,
system enters the RAM back-up state.
The POF instruction is equivalent to the NOP instruction when
the EPOF instruction is not executed before the POF instruction.
As oscillation is stopped retaining RAM, the function of reset
circuit and states at RAM back-up mode, power dissipation can
be reduced without losing the contents of RAM.
Table 13 shows the function and states retained at RAM back-
up. Figure 29 shows the state transition.
(1) Identification of the start condition
Warm start (return from the RAM back-up mode) or cold start
(return from the normal reset state) can be identified by
examining the state of the power down flag (P) with the SNZP
instruction.
(2) Warm start condition
When the external wakeup signal is input after the system
enters the RAM back-up mode by executing the EPOF and
POF instructions continuously, the CPU starts executing the
software from address 0 in page 0. In this case, the P flag is
“1.”
(3) Cold start condition
The CPU starts executing the software from address 0 in
page 0 when;
• reset pulse is input to RESET pin, or
• reset by watchdog timer is performed, or
• voltage drop detection circuit detects the voltage drop.
In this case, the P flag is “0.”
Table 13 Functions and states retained at RAM back-up
Function
Program counter (PC), registers A, B,
carry flag (CY), stack pointer (SP) (Note 2)
RAM back-up
!
Contents of RAM
O
Port level
O
Clock control register MR
O
Timer control register W1
!
Timer control registers W2, W3
O
Timer count value store register W5
O
Interrupt control registers V1, V2
!
Interrupt control register I1
O
Carrier wave output control register C2
!
8-bit general-purpose register SI
O
Timer 1 function
!
Timer 2 function
Timer 3 function
Pull-up control register PU0
Key-on wakeup control register K0
External 0 interrupt request flag (EXF0)
Timer 1 interrupt request flag (T1F)
(Note 3)
(Note 3)
O
O
!
!
Timer 2 interrupt request flag (T2F)
Timer 3 interrupt request flag (T3F)
Watchdog timer flag 1 (WDF1)
Watchdog timer flag 2 (WDF2)
Watchdog timer enable flag (WEF)
16-bit timer (WDT)
Interrupt enable flag (INTE)
(Note 3)
(Note 3)
! (Note 4)
! (Note 4)
! (Note 4)
! (Note 4)
!
Notes 1: “O” represents that the function can be retained, and
“!” represents that the function is initialized.
Registers and flags other than the above are undefined
at RAM back-up, and set an initial value after returning.
2: The stack pointer (SP) points the level of the stack
register and is initialized to “1112” at RAM back-up.
3: The state of the timer is undefined.
4: Initialize the watchdog timer with the WRST instruction,
and then execute the EPOF and POF instructions.
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