4570 Datasheet, PDF (17/69 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(7) Interrupt sequence
Interrupts occur only when the respective INTE flag, interrupt
enable bits (V10–V13 and V20–V23), and interrupt request
flags (EXF0, T1F, T2F, T3F) are “1.” The interrupt actually
occurs 2 to 3 machine cycles after the cycle in which all three
conditions are satisfied. The interrupt occurs after 3 machine
cycles only when the three interrupt conditions are satisfied
on execution of instructions other than one-cycle instructions
(Refer to Figure 16).
q When an interrupt request flag is set after its interrupt is enabled (Note 1)
f(XIN)
System clock=f(X IN)/4 selected
1 machine cycle
T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3
T1 T2 T3
f(XIN)
System clock=f(X IN) selected
Interrupt enable
flag (INTE)
T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3
T1 T2 T3
EI instruction
execution cycle
Interrupt enabled state
Interrupt disabled state
External
interrupt
INT pin
Flag
EXF0
Timer 1,
timer 2,
timer 3
interrupts
Flag
T1F, T2F
T3F
Retaining level for 4 cycles or
more of f(XIN) is necessary.
Interrupt activated
condition satisfied
Flag cleared
2 to 3 machine cycles
(Notes 2, 3)
Software starts
from interrupt address.
Notes 1: The system clock = f(X IN)/4 is selected just after system is released from reset.
2: The address is stacked to the last cycle.
3: This interval of cycles depends on the instruction executed at the time when each
interrupt activated condition is satisfied.
Fig. 16 Interrupt sequence
16