PD17P709A_15 Datasheet, PDF (31/38 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLER WITH DEDICATED HARDWARE FOR DIGITAL TUNING SYSTEM

µPD17P709A
AC Programming Characteristics (TA = 25°C, VDD = 6.0 ±0.25 V, VPP = 12.5 ±0.5 V)
Parameter
Symbol
Conditions
Address setup time^Note (to MD0↓)
tAS
MD1 setup time (to MD0↓)
tM1S
Data setup time (to MD0↓)
tDS
Address hold time^Note (from MD0↑)
tAH
Data hold time (from MD0↑)
tDH
Delay time from MD0↑ to data output float tDF
VPP setup time (to MD3↑)
tVPS
VDD setup time (to MD3↑)
tVDS
Initial program pulse width
tPW
Additional program pulse width
tOPW
MD0 setup time (to MD1↑)
tM0S
Delay time from MD0↓ to data output tDV
MD0 = MD1 = VIL
MD1 hold time (from MD0↑)
tM1H
tM1H + tM1R ≥ 50 µs
MD1 recovery time (from MD0↓)
tM1R
Program counter reset time
tPCR
CLK input high-/low-level widths
tXH, tXL
CLK input frequency
fX
Initial mode setting time
tI
MD3 setup time (to MD1↑)
tM3S
MD3 hold time (from MD1↓)
tM3H
MD3 setup time (to MD0↓)
tM3SR Program memory read
Delay time from address^Note to data output tDAD
Program memory read
Hold time from address^Note to data output tHAD
Program memory read
MD3 hold time (from MD0↑)
tM3HR Program memory read
Delay time from MD3↓ to data output float tDFR
Program memory read
Reset setup time
tRES
MIN.
2
2
2
2
2
0
2
2
0.95
0.95
2
2
2
10
0.125
2
2
2
2
0
2
10
TYP.
1.0
MAX.
130
1.05
21.0
1
4.19
2
130
2
Unit
µs
µs
µs
µs
µs
ns
µs
µs
ms
ms
µs
µs
µs
µs
µs
µs
MHz
µs
µs
µs
µs
µs
ns
µs
µs
µs
Note The internal address signal is incremented by 1 on the 3rd fall of a four-clock input (CLK) cycle, and is not
connected to a pin.
Data Sheet U15723EJ1V0DS
29