PD17P709A_15 Datasheet, PDF (13/38 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLER WITH DEDICATED HARDWARE FOR DIGITAL TUNING SYSTEM

µPD17P709A
Pin No. Symbol
30
VDD1
79
VDD0
31 VCOH
32 VCOL
Function
Power supply. Supply the same voltage to these pins.
• With CPU and peripheral function operating: 4.5 to 5.5 V
• With CPU operating:
3.5 to 5.5 V
• With clock stopped:
2.2 to 5.5 V
PLL local oscillation (VCO) frequency input.
• VCOH
• Active with VHF mode selected by program; otherwise, pulled down.
• VCOL
• Active with HF or MW mode selected by program; otherwise, pulled down.
Output Form
–
–
Because the input of these pins goes into an AC amplifier, cut the DC
component of the input signal with a capacitor.
34 EO0
35 EO1
Output from charge pump of PLL frequency synthesizer. Outputs the divided
frequency of local oscillation and the result of comparison of the phase
difference of the reference frequency.
CMOS
3-state
After reset
With clock stopped
Power-on reset WDT&SP reset
CE reset
High-impedance
output
High-impedance
output
High-impendance High-impedance
output
output
36 TEST
Test input pin.
–
Be sure to connect this pin to GND.
37 P1D3
Port 1D and BEEP output.
38 P1D2
• P1D3 to P1D0
39 P1D1/BEEP1 • 4-bit I/O port
40 P1D0/BEEP0 • Input or output can be specified in 1-bit units.
• BEEP1, BEEP0
• BEEP output
CMOS
push-pull
After reset
With clock stopped
Power-on reset WDT&SP reset
CE reset
Input
(P1D3 to P1D0)
Input
(P1D3 to P1D0)
Retained
(P1D3 to P1D0)
Retained
(P1D3 to P1D0)
43 P2B3
|
|
46 P2B0
4-bit I/O port.
Input or output can be specified in 1-bit units.
After reset
CMOS
push-pull
With clock stopped
Power-on reset WDT&SP reset
CE reset
Input
Input
Retained
Retained
47 P3C3
|
|
50 P3C0
4-bit I/O port.
Input or output can be specified in 4-bit units.
After reset
CMOS
push-pull
With clock stopped
Power-on reset WDT&SP reset
CE reset
Input
Input
Retained
Retained
Data Sheet U15723EJ1V0DS
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