HYB18TC512160BF Datasheet, PDF (8/61 Pages) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM

Internet Data Sheet
HYB18TC512[16/80]0BF
512-Mbit Double-Data-Rate-Two SDRAM
Ball#/Pin#
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
Name
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
A13
Pin
Type
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
NC
–
Address Signals ×16 Organization
L2
BA0
I
L3
BA1
I
L1
NC
–
M8
A0
I
M3
A1
I
M7
A2
I
N2
A3
I
N8
A4
I
N3
A5
I
N7
A6
I
P2
A7
I
P8
A8
I
P3
A9
I
M2
A10
I
AP
I
P7
A11
I
R2
A12
I
–
SSTL
SSTL
–
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Function
Address Signal 12:0, Address Signal 10/Autoprecharge
Address Signal 13
Note: x4/x8 512 Mbit components
Note: and x16 512 Mbit components
Bank Address Bus 1:0
Address Signal 12:0, Address Signal 10/Autoprecharge
Rev. 1.11, 2006-09
8
03292006-HDLH-OAY6