HYB18TC512160BF Datasheet, PDF (6/61 Pages) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM

Internet Data Sheet
HYB18TC512[16/80]0BF
512-Mbit Double-Data-Rate-Two SDRAM
1.2
Description
The 512-Mb DDR2 DRAM is a high-speed Double-Data-
Rate-Two CMOS DRAM device containing 536,870,912 bits
and internally configured as a quad-bank DRAM. The 512-Mb
device is organized as either 32 Mbit × 4 I/O ×4 banks,
16 Mbit ×8 I/O × 4 banks or 8 Mbit ×16 I/O ×4 banks chip.
These devices achieve high speed transfer rates starting at
400 Mb/sec/pin for general applications. See Table 1 to
Table 4 for performance figures.
The device is designed to comply with all DDR2 DRAM key
features:
1. Posted CAS with additive latency,
2. Write latency = read latency - 1,
3. Normal and weak strength data-output driver,
4. Off-Chip Driver (OCD) impedance adjustment
5. On-Die Termination (ODT) function.
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are
latched at the cross point of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a single ended
DQS or differential DQS-DQS pair in a source synchronous
fashion.
A 16-bit address bus for ×4 and ×8 organized components
and a 15-bit address bus for ×16 components is used to
convey row, column and bank address information in a RAS-
CAS multiplexing style.
The DDR2 device operates with a 1.8 V ± 0.1 V power
supply. An Auto-Refresh and Self-Refresh mode is provided
along with various power-saving power-down modes.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
The DDR2 SDRAM is available in PG-TFBGA package.
Product Type
Org Speed
HYB18TC512160BF-2.5 ×16
HYB18TC512800BF-2.5 ×8
HYB18TC512160BF-3 ×16
HYB18TC512800BF-3 ×8
HYB18TC512160BF-3S ×16
HYB18TC512800BF-3S ×8
HYB18TC512160BF-3.7 ×16
HYB18TC512800BF-3.7 ×8
HYB18TC512160BF-5 ×16
HYB18TC512800BF-5 ×8
1) CAS: Column Address Strobe
2) RCD: Row Column Delay
3) RP: Row Precharge
DDR2-800E
DDR2-800E
DDR2-667C
DDR2-667C
DDR2-667D
DDR2-667D
DDR2-533C
DDR2-533C
DDR2-400B
DDR2-400B
TABLE 5
Ordering Information for RoHS compliant products
CAS-RCD-RP
Latencies¹⁾²⁾³⁾
Clock CAS-RCD-RP
(MHz) Latencies¹⁾²⁾³⁾
Clock Package
(MHz)
6-6-6
6-6-6
4-4-4
4-4-4
5-5-5
5-5-5
4-4-4
4-4-4
3-3-3
3-3-3
400 5-5-5
400 5-5-5
333 3-3-3
333 3-3-3
333 4-4-4
333 4-4-4
266 3-3-3
266 3-3-3
200 —
200 —
333 PG-TFBGA-84-8
333 PG-TFBGA-60-24
200 PG-TFBGA-84-8
200 PG-TFBGA-60-24
266 PG-TFBGA-84-8
266 PG-TFBGA-60-24
200 PG-TFBGA-84-8
200 PG-TFBGA-60-24
—
PG-TFBGA-84-8
—
PG-TFBGA-60-24
Note: For product nomenclature see Chapter 9 of this data sheet
Rev. 1.11, 2006-09
6
03292006-HDLH-OAY6