HYB18TC512160BF Datasheet, PDF (15/61 Pages) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM

Internet Data Sheet
2.2
512 Mbit DDR2 Addressing
This chapter contents the table for the 512 Mbit DDR2 Addressing.
Configuration
Bank Address
Number of Banks
Auto-Precharge
Row Address
Column Address
Number of Column Address Bits
Number of I/Os
Page Size [Bytes]
1) Referred to as ’org’
2) Referred to as ’colbits’
3) PageSize = 2^colbits × org/8 [Bytes]
64Mb x 8¹⁾
BA[1:0]
4
A10 / AP
A[13:0]
A[9:0]
10
8
1024 (1K)
HYB18TC512[16/80]0BF
512-Mbit Double-Data-Rate-Two SDRAM
TABLE 9
DDR2 Addressing for ×8 Organization
Note
2)
3)
Configuration
Bank Address
Number of Banks
Auto-Precharge
Row Address
Column Address
Number of Column Address Bits
Number of I/Os
Page Size [Bytes]
1) Referred to as ’org’
2) Referred to as ’colbits’
3) PageSize = 2^colbits × org/8 [Bytes]
32Mb x 16¹⁾
BA[1:0]
4
A10 / AP
A[12:0]
A[9:0]
10
16
2048 (2K)
TABLE 10
DDR2 Addressing for ×16 Organization
Note
2)
3)
Rev. 1.11, 2006-09
15
03292006-HDLH-OAY6