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HYB18TC512160BF Datasheet, PDF (36/61 Pages) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM | |||
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Internet Data Sheet
HYB18TC512[16/80]0BF
512-Mbit Double-Data-Rate-Two SDRAM
7
Timing Characteristics
This chapter contains speed grade definition, AC timing parameter and ODT tables.
7.1
Speed Grade Definitions
All Speed grades faster than DDR2-DDR400B comply with DDR2-DDR400B timing specifications(tCK = 5ns with tRAS = 40ns).
List of Speed Grade Definition tables:
⢠Table 38 âSpeed Grade Definition Speed Bins for DDR2â800Eâ on Page 36
⢠Table 39 âSpeed Grade Definition Speed Bins for DDR2â667â on Page 37
⢠Table 41 âSpeed Grade Definition Speed Bins for DDR2â400Bâ on Page 38
Speed Grade
TABLE 38
Speed Grade Definition Speed Bins for DDR2â800E
DDR2â800E
Unit
Note
IFX Sort Name
â2.5
CAS-RCD-RP latencies
6â6â6
tCK
Parameter
Symbol
Min.
Max.
â
Clock Frequency
@ CL = 3
tCK
5
8
ns
1)2)3)4)
@ CL = 4
tCK
3.75
8
ns
1)2)3)4)
@ CL = 5
tCK
3
8
ns
1)2)3)4)
@ CL = 6
tCK
2.5
8
ns
1)2)3)4)
Row Active Time
tRAS
45
70000
ns
1)2)3)4)5)
Row Cycle Time
tRC
60
â
ns
1)2)3)4)
RAS-CAS-Delay
tRCD
15
â
ns
1)2)3)4)
Row Precharge Time
tRP
15
â
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) under the âReference Load for Timing Measurementsâ.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode; The input reference level for signals other than CK/CK, DQS / DQS,
RDQS / RDQS is defined.
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
Rev. 1.11, 2006-09
36
03292006-HDLH-OAY6
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