HYB18TC512160BF Datasheet, PDF (7/61 Pages) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM

Internet Data Sheet
HYB18TC512[16/80]0BF
512-Mbit Double-Data-Rate-Two SDRAM
2
Pin Configuration
This chapter contains the pin configuration tables.
2.1
CPin Configuration for TFBGA–60 TFBGA–84
The pin configuration of a DDR2 SDRAM is listed by function in Table 6. The abbreviations used in the Pin# and Buffer Type
columns are explained in Table 7 and Table 8 respectively. The pin numbering for the FBGA package is depicted in Figure 1
for ×4, Figure 2 for ×8 and Figure 3 for ×16.
Ball#/Pin#
Name
Pin
Type
Clock Signals ×8 Organization
E8
CK
I
F8
CK
I
F2
CKE
I
Clock Signals ×16 Organization
J8
CK
I
K8
CK
I
K2
CKE
I
Control Signals ×8 Organization
F7
RAS
I
G7
CAS
I
F3
WE
I
G8
CS
I
Control Signals ×16 Organization
K7
RAS
I
L7
CAS
I
K3
WE
I
L8
CS
I
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Function
TABLE 6
Pin Configuration of DDR2 SDRAM
Clock Signal CK, Complementary Clock Signal CK
Clock Enable
Clock Signal CK, Complementary Clock Signal CK
Clock Enable
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
Chip Select
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
Chip Select
G2
BA0
I
SSTL
Bank Address Bus 1:0
G3
BA1
I
SSTL
Rev. 1.11, 2006-09
7
03292006-HDLH-OAY6