HYB18TC512160BF Datasheet, PDF(14/61 Page) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM

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HYB18TC512160BF Datasheet, PDF (14/61 Pages) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM

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Internet Data Sheet

HYB18TC512[16/80]0BF

512-Mbit Double-Data-Rate-Two SDRAM

FIGURE 3

Pin Configuration for Ã16 components, PG-TFBGA-84-8

6''

'4

.#

6664

66 6

8'0

6'' 4

'4

6'' 4

'4

6664

'4

6''

1&

66 6

'4

6664

/'0

6'' 4

'4

6'' 4

'4

6' '/

6664

65( )

'4

66 6

&.(

:(

$

666 4

8'46

6'' 4

%

8'46

666 4

'4

&

6'' 4

'4

6'' 4

'

'4

666 4

'4

(

666 4

/'46

6'' 4

)

/'46

666 4

'4

*

6'' 4

'4

6'' 4

+

'4

666 4

'4

-

966 '/ &.

6''

.

5$6

&.

2' 7

1&

%$

%$

/

&$6

&6

$ $3 $

0

$

$

6''

66 6

$

$

1

$

$

$

$

3

$

$

666

6''

$

1&

5

1&

1&

03 37

Notes

1. UDQS/UDQS is data strobe for DQ[15:8], LDQS/LDQS is

data strobe for DQ[7:0]

2. LDM is the data mask signal for DQ[7:0], UDM is the data

mask signal for DQ[15:8]

3. VDDL and VSSDL are power and ground for the DLL. VDDL is

connected to VDD on the device. VDD, VDDQ, VSSDL, VSS,

and VSSQ are isolated on the device.

Rev. 1.11, 2006-09

14

03292006-HDLH-OAY6

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