HYB18TC512160BF Datasheet, PDF (11/61 Pages) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM

Internet Data Sheet
HYB18TC512[16/80]0BF
512-Mbit Double-Data-Rate-Two SDRAM
Ball#/Pin#
Name
Pin
Type
Not Connected ×4 Organization
A2, B1, B9, D1, NC
NC
D9,G1, L3,L7,
L8
Not Connected ×8 Organization
G1, L3,L7, L8 NC
NC
Not Connected ×16 Organization
A2, E2, L1, R3, NC
NC
R7, R8
Other Pins ×8 Organization
F9
ODT
I
Other Pins ×16 Organization
K9
ODT
I
Buffer
Type
–
–
–
SSTL
SSTL
Function
Not Connected
Not Connected
Not Connected
On-Die Termination Control
On-Die Termination Control
Abbreviation
I
O
I/O
AI
PWR
GND
NC
Description
Standard input-only pin. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
Ground
Not Connected
TABLE 7
Abbreviations for Pin Type
Abbreviation
SSTL
LV-CMOS
CMOS
OD
TABLE 8
Abbreviations for Buffer Type
Description
Serial Stub Terminated Logic (SSTL_18)
Low Voltage CMOS
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
Rev. 1.11, 2006-09
11
03292006-HDLH-OAY6