HYB18TC1G800AF Datasheet, PDF (6/54 Pages) Qimonda AG – 1-Gbit DDR2 SDRAM

Internet Data Sheet
2
Pin Configuration
HYB18TC1G[80/16]0AF
1-Gbit DDR2 SDRAM
This chapter contains the pin configuration.
2.1
Pin Configuration for TFBGA–68
The pin configuration of a DDR2 SDRAM is listed by function in Table 5. The abbreviations used in the Pin# and Buffer Type
columns are explained in Table 6 and Table 7 respectively. The pin numbering for the FBGA package is depicted in Figure 1
for ×8 components.
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Clock Signals ×8 Organizations
J8
CK
I
K8
CK
I
K2
CKE
I
Control Signals ×8 Organizations
K7
RAS
I
L7
CAS
I
K3
WE
I
L8
CS
I
Address Signals ×8 Organizations
L2
BA0
I
L3
BA1
I
L1
BA2
I
M8
A0
I
M3
A1
I
M7
A2
I
N2
A3
I
N8
A4
I
N3
A5
I
N7
A6
I
P2
A7
I
P8
A8
I
P3
A9
I
M2
A10
I
AP
I
P7
A11
I
R2
A12
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Function
TABLE 5
Pin Configuration of DDR2 SDRAM
Clock Signal CK, Complementary Clock Signal CK
Clock Enable
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
Chip Select
Bank Address Bus 2:0
Address Signal 12:0, Address Signal 10/Autoprecharge
Rev. 1.11, 2006-09
6
03292006-PJAE-UQLG