HYB18TC1G800AF Datasheet, PDF (13/54 Pages) Qimonda AG – 1-Gbit DDR2 SDRAM

Internet Data Sheet
HYB18TC1G[80/16]0AF
1-Gbit DDR2 SDRAM
FIGURE 2
Pin Configuration for ×16 components, P-TFBGA-92 (top view)









1&  1& 
$
1& 1& 
%
&
9_'_{' }
1& 
9₆_{6 }
'4   ^96^64  8' 0
9_'_{' 4  '4 } 9_'_{' 4 }
'4   ^96^64  '4  
9_'_{' }
1& 
9₆_{6 }
'4   ^96^64  /'0 
9_'_{' 4  '4 } 9_'_{' 4 }
'4   ^96^64  '4 
9_'_{' / } 9₅_{( ) }
9₆_{6 }
&. ( :(
'
9₆_{64 8' 4 6 } 9_'_{' 4 }
(
8' 4 6  ^96^64  '4  
)
9_'_{' 4  '4  } 9_'_{' 4 }
*
'4   ^96^64  '4  
+
9₆_{64 /'4 6 } 9_'_{' 4 }
-
/'4 6  ^96^64  '4  
.
9_'_{' 4  '4  } 9_'_{' 4 }
/
'4   ^96^64  '4  
0
9₆_{6'/ } &.
9_'_{' }
1
5$ 6 &. 2' 7 
%$  %$  %$ 
$$ 3 $
9₆_{6 }
$
$
$ $
9_'_{'  $ 1& }
3
&$ 6 &6
5
$
$
9_'_{' }
7
$ $
8
$ $ ^96^6
9
1&  1&
:
;
1&  1& 
$$
1& 1& 
03 37
Notes
1. UDQS/UDQS is data strobe for upper byte, LDQS/LDQS
is data strobe for lower byte
2. UDM is the data mask signal for the upper byte
UDQ0~UDQ7, LDM is the data mask signal for the lower
byte LDQ0~LDQ7
Rev. 1.11, 2006-09
13
03292006-PJAE-UQLG