HYB18TC1G800AF Datasheet, PDF (10/54 Pages) Qimonda AG – 1-Gbit DDR2 SDRAM

Internet Data Sheet
HYB18TC1G[80/16]0AF
1-Gbit DDR2 SDRAM
2.2
Pin Configuration for TFBGA-92
The pin configuration of a DDR2 SDRAM is listed by function in Table 8. The abbreviations used in the Pin#/Buffer Type
columns are explained in Table 9 and Table 10 respectively. The pin numbering for the FBGA package is depicted in Figure 2
for ×16 components.
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Clock Signals ×16 Organization
J8
CK
I
K8
CK
I
K2
CKE
I
Control Signals ×16 Organization
K7
RAS
I
L7
CAS
I
K3
WE
I
L8
CS
I
Address Signals ×16 Organization
L2
BA0
I
L3
BA1
I
L1
BA2
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
NC
–
–
M8
A0
I
SSTL
M3
A1
I
SSTL
M7
A2
I
SSTL
N2
A3
I
SSTL
N8
A4
I
SSTL
N3
A5
I
SSTL
N7
A6
I
SSTL
P2
A7
I
SSTL
P8
A8
I
SSTL
P3
A9
I
SSTL
M2
A10
I
SSTL
AP
I
SSTL
P7
A11
I
SSTL
R2
A12
I
SSTL
Function
TABLE 8
Pin Configuration of DDR SDRAM
Clock Signal CK, Complementary Clock Signal CK
Clock Enable
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
Chip Select
Bank Address Bus 1:0
Bank Address Bus 2
Note: 1 Gbit components and higher
Note: 256 Mbit and 512 Mbit components
Address Signal 12:0,Address Signal 10/Autoprecharge
Rev. 1.11, 2006-09
10
03292006-PJAE-UQLG