HYB18TC1G800AF Datasheet, PDF (15/54 Pages) Qimonda AG – 1-Gbit DDR2 SDRAM

Internet Data Sheet
HYB18TC1G[80/16]0AF
1-Gbit DDR2 SDRAM
Field Bits Type¹⁾
Description
CL
[6:4] w
CAS Latency
Note: All other bit combinations are illegal.
BT
3
w
BL
[2:0] w
011_B CL 3
100_B CL 4
101_B CL 5
110_B CL 6
111_B CL 7
Burst Type
0_B BT Sequential
1_B BT Interleaved
Burst Length
Note: All other bit combinations are illegal.
010_B BL 4
011_B BL 8
1) w = write only register bits
2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing t_WR (in ns) by t_CK (in ns) and
rounding up to the next integer: WR [cycles] ≥ t_WR (ns) / t_CK (ns). The mode register must be programmed to fulfill the minimum requirement
for the analogue t_WR timing WR_MIN is determined by t_CK.MAX and WR_MAX is determined by t_CK.MIN.
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5_W_W
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Z Z
Z
Z
Z
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Field
BA2
BA1
BA0
Bits Type¹⁾
16 reg. addr.
15
14
TABLE 12
Extended Mode Register Definition (BA[2:0] = 001B)
Description
Bank Address [2]
Note: BA2 not available on 256 Mbit and 512 Mbit components
0_B BA2 Bank Address
Bank Address [1]
0_B BA1 Bank Address
Bank Address [0]
0_B BA0 Bank Address
Rev. 1.11, 2006-09
15
03292006-PJAE-UQLG