HYB18TC1G800AF Datasheet, PDF (5/54 Pages) Qimonda AG – 1-Gbit DDR2 SDRAM

Internet Data Sheet
HYB18TC1G[80/16]0AF
1-Gbit DDR2 SDRAM
1.2
Description
The 1-Gb DDR2 DRAM is a high-speed Double-Data-Rate-
Two CMOS Synchronous DRAM device containing
1,073,741,824 bits and internally configured as anoctal quad-
bank DRAM. The 1-Gb device is organized as either 16 Mbit
×8 I/O ×8 banks or 8 Mbit ×16 I/O ×8 banks chip. These
synchronous devices achieve high speed transfer rates
starting at 400 Mb/sec/pin for general applications. See
Table 1 to Table 3 for performance figures.
The device is designed to comply with all DDR2 DRAM key
features:
1. Posted CAS with additive latency
2. Write latency = read latency - 1
3. Normal and weak strength data-output driver
4. Off-Chip Driver (OCD) impedance adjustment
5. On-Die Termination (ODT) function
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are
latched at the cross point of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a single ended
DQS or differential DQS-DQS pair in a source synchronous
fashion.
A 17 bit address bus for ×4 and ×8 organised components
and a 16 bit address bus for ×16 components is used to
convey row, column and bank address information in aRAS-
CAS multiplexing style.
The DDR2 device operates with a 1.8 V ± 0.1 V power
supply. An Auto-Refresh and Self-Refresh mode is provided
along with various power-saving power-down modes.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
The DDR2 SDRAM is available in PG-TFBGA package.
Product Type
Org. Speed
HYB18TC1G160BF–3S ×16
HYB18TC1G800BF–3S ×8
HYB18TC1G160BF–3.7 ×16
HYB18TC1G800BF–3.7 ×8
HYB18TC1G160BF–5
×16
HYB18TC1G800BF–5
×8
1) CAS: Column Address Strobe
2) RCD: Row Column Delay
3) RP: Row Precharge
DDR2–667D
DDR2–667D
DDR2–533C
DDR2–533C
DDR2–400B
DDR2–400B
TABLE 4
Ordering Information for RoHS compliant products
CAS-RCD-RP Latencies¹⁾²⁾³⁾ Clock (MHz) Package
5–5–5
5–5–5
4–4–4
4–4–4
3–3–3
3–3–3
333
PG–TFBGA–92–1
333
PG–TFBGA–68–3
266
PG–TFBGA–92–1
266
PG–TFBGA–68–3
200
PG–TFBGA–92–1
200
PG–TFBGA–68–3
Note: For product nomenclature see Chapter 9 of this data sheet
Rev. 1.11, 2006-09
5
03292006-PJAE-UQLG