HYB18TC1G800AF Datasheet, PDF (28/54 Pages) Qimonda AG – 1-Gbit DDR2 SDRAM

Internet Data Sheet
HYB18TC1G[80/16]0AF
1-Gbit DDR2 SDRAM
TABLE 30
OCD Default Characteristics
Symbol Description
Min.
Nominal
Max.
Unit
Note
—
Output Impedance
Ohms
1)2)
—
Pull-up / Pull down mismatch
0
—
4
Ohms
1)2)3)
—
Output Impedance step size
0
for OCD calibration
—
1.5
Ohms ⁴⁾
S_OUT
Output Slew Rate
1.5
—
5.0
V / ns
1)5)6)7)8)
1) Absolute Specifications (T_OPER; V_DD = 1.8 V ± 0.1 V; VDDQ = 1.8 V ± 0.1 V), altering OCD from default state no longer requires DRAM to
meet timing, voltage and slew rate specifications on I/O’s.
2) Impedance measurement condition for output source dc current: V_DDQ = 1.7 V, V_OUT = 1420 mV; (V_OUT–V_DDQ) / I_OH must be less than 23.4
ohms for values of V_OUT between V_DDQ and V_DDQ – 280 mV. Impedance measurement condition for output sink dc current: V_DDQ = 1.7 V;
V_OUT = –280 mV; V_OUT / I_OL must be less than 23.4 Ohms for values of V_OUT between 0 V and 280 mV.
3) Mismatch is absolute value between pull-up and pull-down, both measured at same temperature and voltage.
4) This represents the step size when the OCD is near 18 ohms at nominal conditions across all process parameters and represents only the
DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18 ± 0.75 Ohms under nominal
conditions.
5) Slew Rates according to V_IL(ac) to V_IH(ac).
6) The absolute value of the Slew Rate as measured from DC to DC is equal to or greater than the Slew Rate as measured from AC to AC.
This is verified by design and characterization but not subject to production test.
7) Timing skew due to DRAM output Slew Rate mis-match between DQS / DQS and associated DQ’s is included in t_DQSQ and t_QHS
specification.
8) DRAM output Slew Rate specification applies to 400 and 533 speed bins.
5.5
Input / Output Capacitance
Symbol Parameter
CCK
CDCK
CI
CDI
CIO
CDIO
Input capacitance, CK and CK
Input capacitance delta, CK and CK
Input capacitance, all other input-only pins
Input capacitance delta, all other input-only pins
Input/output capacitance,
DQ, DM, DQS, DQS, RDQS, RDQS
Input/output capacitance delta,
DQ, DM, DQS, DQS, RDQS, RDQS
TABLE 31
Input / Output Capacitance
DDR2-400 & DDR- DDR2-667
Unit
2-533
Min. Max.
Min.
Max.
1.0
2.0
1.0
2.0
pF
—
0.25
—
0.25
pF
1.0
2.0
1.0
2.0
pF
—
0.25
—
0.25
pF
2.5
4.0
2.5
3.5
pF
—
0.5
—
0.5
pF
Rev. 1.11, 2006-09
28
03292006-PJAE-UQLG