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HYB18TC1G800AF Datasheet, PDF (11/54 Pages) Qimonda AG – 1-Gbit DDR2 SDRAM
Internet Data Sheet
HYB18TC1G[80/16]0AF
1-Gbit DDR2 SDRAM
Ball#/Pin#
Name
Pin
Type
Data Signals ×16 Organization
G8
DQ0
I/O
G2
DQ1
I/O
H7
DQ2
I/O
H3
DQ3
I/O
H1
DQ4
I/O
H9
DQ5
I/O
F1
DQ6
I/O
F9
DQ7
I/O
C8
DQ8
I/O
C2
DQ9
I/O
D7
DQ10
I/O
D3
DQ11
I/O
D1
DQ12
I/O
D9
DQ13
I/O
B1
DQ14
I/O
B9
DQ15
I/O
Data Strobe ×16 Organization
B7
UDQS I/O
A8
UDQS I/O
F7
LDQS I/O
E8
LDQS I/O
Data Mask ×16 Organization
B3
UDM
I
F3
LDM
I
Power Supplies ×16 Organization
J2
VREF
E9, G1, G3, G7, VDDQ
G9
AI
PWR
J1
E1, J9, M9, R1
E7, F2, F8, H2,
H8
VDDL
VDD
VSSQ
PWR
PWR
PWR
J7
VSSDL
PWR
J3,N1,P9
VSS
PWR
Not Connected ×16 Organization
A2, E2, L1, R3, NC
NC
R7, R8
Other Pins ×16 Organization
K9
ODT
I
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
–
–
–
–
–
–
–
–
SSTL
Function
Data Signal 15:0
Note: Bi-directional data bus. DQ[15:0] for ×16 components.
Data Strobe Upper Byte
Data Strobe Lower Byte
Data Mask Upper Byte
Data Mask Lower Byte
I/O Reference Voltage
I/O Driver Power Supply
Power Supply
Power Supply
Power Supply
Power Supply
Power Supply
Not Connected
On-Die Termination Control
Rev. 1.11, 2006-09
11
03292006-PJAE-UQLG