HYB18TC1G800AF Datasheet, PDF (31/54 Pages) Qimonda AG – 1-Gbit DDR2 SDRAM

Internet Data Sheet
HYB18TC1G[80/16]0AF
1-Gbit DDR2 SDRAM
6
Currents Specifications and Conditions
For Double-Data-Rate-Two SDRAMs described in this data
sheet the maximum I_DD values are listed in Table 36. The
measurement conditions for I_DD characteristics are listed in
Table 34, general timing conditions used are listed in
Table 35. At the end of this chapter the on-die-termination
currents are defined.
TABLE 34
I_DD Measurement Conditions
Parameter
Symbol Note
Operating Current - One bank Active - Precharge
I_DD0
t_CK = t_CK(IDD), t_RC = t_RC(IDD), t_RAS = t_RAS.MIN(IDD), CKE is HIGH, CS is HIGH between valid commands.
Address and control inputs are switching; Databus inputs are switching.
Operating Current - One bank Active - Read - Precharge
I_DD1
I_OUT = 0 mA, BL = 4, t_CK = t_CK(IDD), t_RC = t_RC(IDD), t_RAS = t_RAS.MIN(IDD), t_RCD = t_RCD(IDD), AL = 0, CL =
CL(IDD); CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are
switching; Databus inputs are switching.
Precharge Power-Down Current
All banks idle; CKE is LOW; t_CK = t_CK(IDD);Other control and address inputs are stable; Data bus inputs
are floating_.
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH; t_CK = t_CK(IDD); Other control and address inputs are switching,
Data bus inputs are switching_.
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH; t_CK = t_CK(IDD); Other control and address inputs are stable,
Data bus inputs are floating.
I_DD2P
I_DD2N
I_DD2Q
Active Power-Down Current
All banks open; t_CK = t_CK(IDD), CKE is LOW; Other control and address inputs are stable; Data bus
inputs are floating. MRS A12 bit is set to “0” (Fast Power-down Exit).
I_DD3P(0)
Active Power-Down Current
All banks open; t_CK = t_CK(IDD), CKE is LOW; Other control and address inputs are stable, Data bus
inputs are floating. MRS A12 bit is set to 1 (Slow Power-down Exit);
I_DD3P(1)
Active Standby Current
I_DD3N
All banks open; t_CK = t_CK(IDD); t_RAS = t_RAS.MAX(IDD), t_RP = t_RP(IDD); CKE is HIGH, CS is HIGH between valid
commands. Address inputs are switching; Data Bus inputs are switching;
Operating Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL_(IDD); t_CK = t_CK(IDD); t_RAS
= t_{RAS.MAX.(IDD)}, t_RP = t_RP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are
switching; Data Bus inputs are switching; I_OUT = 0 mA.
Operating Current
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL_(IDD); t_CK = t_CK(IDD); t_RAS
= t_RAS.MAX(IDD), t_RP = t_RP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are
switching; Data Bus inputs are switching;
I_DD4R
I_DD4W
Burst Refresh Current
I_DD5B
t_CK = t_CK(IDD), Refresh command every t_RFC = t_RFC(IDD) interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are switching, Data bus inputs are switching.
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Rev. 1.11, 2006-09
31
03292006-PJAE-UQLG