HYB18TC1G800AF Datasheet, PDF (17/54 Pages) Qimonda AG – 1-Gbit DDR2 SDRAM

Internet Data Sheet
HYB18TC1G[80/16]0AF
1-Gbit DDR2 SDRAM
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Field Bits
Type¹⁾
TABLE 13
EMRS(2) Programming Extended Mode register Definition (BA[2:0]=010_B)
Description
BA2 16
w
Bank Address[2]
Note: BA2 is not available on 256 Mbit and 512 Mbit components
BA [15:14] w
A
[13:7] w
0_B BA2 Bank Address
Bank Adress[15:14]
00_B BA MRS
01_B BA EMRS(1)
10_B BA EMRS(2)
11_B BA EMRS(3): Reserved
Address Bus[13:0]
Note: A13 is not available for 256 Mbit and ×16 512 Mbit configuration
0_B A[13:0] Address bits
A
7
w
Address Bus[7], adapted self refresh rate for T_CASE > 85°C
0_B A7 disable
1_B A7 enable ²⁾
A
[6:4] w
Address Bus[6:4]
0_B A[6:4] Address bits
A
3
w
Address Bus[3], Duty Cycle Correction (DCC)
0_B A[3] DCC disabled
1_B A[3] DCC enabled
Partial Self Refresh for 8 banks
A
[2:0] w
Address Bus[2:0], Partial Array Self Refresh for 8 Banks³⁾
000_B PASR0 Full Array
001_B PASR1 Half Array (BA[2:0]=000, 001, 010 & 011)
010_B PASR2 Quarter Array (BA[2:0]=000, 001)
011_B PASR3 1/8 array (BA[2:0] = 000)
100_B PASR4 3/4 array (BA[2:0]= 010, 011, 100, 101, 110 & 111)
101_B PASR5 Half array (BA[2:0]=100, 101, 110 & 111)
110_B PASR6 Quarter array (BA[2:0]= 110 & 111)
111_B PASR7 1/8 array(BA[2:0]=111)
1) w = write only
2) When DRAM is operated at 85°C ≤ T_Case ≤ 95°C the extended self refresh rate must be enabled by setting bit A7 to "1" before the self
refresh mode can be entered.
3) If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will be lost if self refresh
is entered. Data integrity will be maintained if t_REF conditions are met and no Self Refresh command is issued
Rev. 1.11, 2006-09
17
03292006-PJAE-UQLG