 English |
|
|
|
|
|
|
|
| HYB18TC1G800AF Datasheet, PDF (51/54 Pages) Qimonda AG – 1-Gbit DDR2 SDRAM | |||
| |||
| ◁ |
Internet Data Sheet
List of Figures
HYB18TC1G[80/16]0AF
1-Gbit DDR2 SDRAM
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Pin Configuration for Ã8 components, P-TFBGA-68 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Configuration for Ã16 components, P-TFBGA-92 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Single-ended AC Input Test Conditions Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Differential DC and AC Input and Output Logic Levels Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AC Overshoot / Undershoot Diagram for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . . . . . . . . . . . 30
Method for calculating transitions and endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Differential input waveform timing - tDS and tDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Differential input waveform timing - tlS and tlH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Package Outline PG-TFBGA-68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Package Pinout P-TFBGA-92 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Rev. 1.11, 2006-09
51
03292006-PJAE-UQLG
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese