HYB18H1G321AF Datasheet, PDF (41/48 Pages) Qimonda AG – GDDR3 Graphics RAM 1-Gbit GDDR3 Graphics RAM

Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
Parameter
CAS
latency
Symbo
l
–10
Limit Values
–11
-14
Unit Note
min
max
min
max
min
max
Power Down Exit time
Other Timing Parameters
t_XPN
7
—
7
—
8
—
t_CK
RES to CKE setup timing
t_ATS
10
—
10
—
10
—
ns
RES to CKE hold timing
t_ATH
10
—
10
—
10
—
ns
Termination update Keep Out
t_KO
10
—
10
—
10
—
ns
timing
Rev. ID EMRS to DQ on timing
t_RIDon
—
20
—
20
—
20
ns
REV. ID EMRS to DQ off timing t_RIDoff —
20
—
20
—
20
ns
1) At 1000 MHz speed grade only 1-CS mode is supported
2) DLL on mode
3) Timing is calculated for a clock frequency of 700 MHz
4) t_HP is the lesser of t_CL minimum and t_CH minimum actually applied to the device CLK, CLK inputs
5) This value of t_MRD applies only to the case where the "DLL reset"’ bit is not activated.
6) t_MRD is defined from MRS to any other command then READ.
7) t_RAS,max is 8×t_REFi
8) t_CCD is either for gapless consecutive reads or gapless consecutive writes.
9) WTR and t_WR start at the first rising edge of CLK after the last valid (falling) WDQS edge of the slowest WDQS signal.
10) WTR and t_WR start at the first rising edge of CLK after the last valid (falling) WDQS edge of the slowest WDQS signal.
11) This parameter is defined for commands issued to rank m following rank n where m ≠ n. For all other type of access, standard timing
parameters do apply.
12) Please round up t_RTW to the next integer of t_CK.
13) This parameter is defined per byte
Rev. 0.92, 2007-10
41
06122007-MW7D-3G3M