HYB18H1G321AF Datasheet, PDF (22/48 Pages) Qimonda AG – GDDR3 Graphics RAM 1-Gbit GDDR3 Graphics RAM

Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
FIGURE 10
Extended Mode Register Bitmap for High-Speed Application
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Notes
1. These settings are for debugging purposes only.
2. Default termination values at Power Up.
3. The ODT disable function disables all terminators on the
device.
4. If the user activates bits in the extended mode register in
an optional field, either the optional field is activated (if
option implemented in the device) or no action is taken by
the device (if option not implemented).
5. WR (write recovery time for auto precharge) in clock
cycles is calculated by dividing t_WR (in ns) and rounding up
to the next integer (WR[cycles] = t_WR[ns] / t_CK[ns]). The
mode register must be programmed to this value.
CLK#
CLK
Command
PA
NOP
t_RP
FIGURE 11
Extended Mode Register Set Timing
EMRS
NOP
t_MRD
NOP
A.C.
A.C.: Any command
Don't Care
EMRS: Extended MRS command
PA: PREALL command
Rev. 0.92, 2007-10
22
06122007-MW7D-3G3M