HYB18H1G321AF Datasheet, PDF (23/48 Pages) Qimonda AG – GDDR3 Graphics RAM 1-Gbit GDDR3 Graphics RAM

Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
4.2.1
DLL enable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to
normal operation after having disabled the DLL. (When the device exits self-refresh mode, the DLL is enabled automatically).
Anytime the DLL is enabled, 1000 cycles must occur before a READ command can be issued.
4.2.2
WR
The WR parameter is programmed using the register bits A4, A5 and A7. This integer parameter defines as a number of clock
cycles the Write Recovery time in a Write with Autoprecharge operation.
The following inequality has to be complied with: WR * t_CK ≥ t_WR, where t_CK is the clock cycle time. The high-speed bitmap
supports WR from 7 to 13. The mid-range bitmap provides WR cycles from 4 to 11.
4.2.3
Termination Rtt
The data termination, Rtt, is used to set the value of the internal termination resistors. The GDDR3 DRAM supports ZQ / 4 and
ZQ / 2 termination values. The termination may also be disabled for testing and other purposes. Data -, address - and command
- termination are disabled in parallel. The Termination Rtt are controlled independently from the Output Driver Impedance
values.
4.2.4
Output Driver Impedance
The Output Driver Impedance extended mode register is used to set the value of the data output driver impedance. When the
auto calibration is used, the output driver impedance is set nominally to ZQ / 6.
If the Output Driver Impedance is changed to 35, 40 or 45 Ohms the user needs to issue 16 AREF commands separated by
t_RFC consecutively to make the change effective. The user must be aware that the Command bus needs to be stable for a time
of t_KO after each AREF.
4.2.5
Vendor Code and Revision Identification
The Manufacturer Vendor Code is selected by issuing an Extended Mode Register Set command with bit A10 set to 1 and bits
A0-A9 and A11 set to the desired value. When the Vendor Code function is enabled the GDDR3 DRAM will provide the
Qimonda vendor code on DQ[3:0] and the revision identification on DQ[7:4]. The code will be driven onto the DQ bus after t_RIDon
following the EMRS command that sets A10 to 1. The Vendor Code and Revision ID will be driven on DQ[7:0] until a new EMRS
command is issued with A10 set back to 0. After t_RIDoff following the second EMRS command, the data bus is driven back to
HIGH. This second EMRS command must be issued before initiating any subsequent operation. Violating this requirement will
result in unspecified operation.
Revision Identification
DQ[7:4]
0011
TABLE 9
Revision ID and Vendor Code
Qimonda Vendor Code
DQ[3:0]
0010
Note: Please refer to Revision Release Note for Revision ID value.
Rev. 0.92, 2007-10
23
06122007-MW7D-3G3M