HYB18H1G321AF Datasheet, PDF (4/48 Pages) Qimonda AG – GDDR3 Graphics RAM 1-Gbit GDDR3 Graphics RAM

Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
1.2
Description
The Qimonda 1-Gbit GDDR3 Graphics RAM is a high speed memory device, designed for high bandwidth intensive
applications like PC graphics systems. The chip is programmable into two different configurations. In the default mode the
architecture is organized as two 512 Mbit memories of 8 banks, each (two CS mode). In an alternate configuration, it behaves
as a conventional, 8-bank 1 Gbit DRAM (one CS mode). Note that at 1000 MHz speed grade only one CS mode is supported.
HYB18H1G321AF–10/11/14 uses a double data rate interface and a 4n-pre fetch architecture. The GDDR3 interface transfers
two 32 bit wide data words per clock cycle to/from the I/O pins. Corresponding to the 4n-pre fetch a single write or read access
consists of a 128 bit wide, one-clock-cycle data transfer at the internal memory core and four corresponding 32 bit wide, one-
half-clock-cycle data transfers at the I/O pins.
Single-ended unidirectional Read and Write Data strobes are transmitted simultaneously with Read and Write data respectively
in order to capture data properly at the receivers of both the Graphics SDRAM and the controller. Data strobes are organized
per byte of the 32 bit wide interface. For read commands the RDQS are edge-aligned with data, and the WDQS are center-
aligned with data for write commands.
The HYB18H1G321AF–10/11/14 operates from a differential clock (CLK and CLK). Commands (addresses and control
signals) are registered at every positive edge of CLK. Input data is registered on both edges of WDQS, and output data is
referenced to both edges of RDQS.
In this document references to “the positive edge of CLK” imply the crossing of the positive edge of CLK and the negative edge
of CLK. Similarly, the “negative edge of CLK” refers to the crossing of the negative edge of CLK and the positive edge of CLK.
References to RDQS are to be interpreted as any or all RDQS<3:0>. WDQS, DM and DQ should be interpreted in a similar
fashion.
Read and write accesses to the HYB18H1G321AF–10/11/14 are burst oriented. The burst length is fixed to 4 and 8 and the
two least significant bits of the burst address are “Don’t Care” and internally set to LOW. Accesses begin with the registration
of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident
with the ACTIVATE command are used to select the bank and the row to be accessed. The address bits registered coincident
with the READ or WRITE command are used to select the bank and the column location for the burst access. In two CS mode,
each of the 2 x 8 banks consists of 4096 row locations and 512 column locations. In one CS mode, the number of row locations
doubles to 8192 rows while the number of column location remains unchanged at 512 columns. An AUTO PRECHARGE
function can be combined with READ and WRITE to provide a self-timed row precharge that is initiated at the end of the burst
access. The pipe lined, multibank architecture of the HYB18H1G321AF–10/11/14 allows for concurrent operation, thereby
providing high effective bandwidth by hiding row precharge and activation time.
The “On Die Termination” interface (ODT) is optimized for high frequency digital data transfers and is internally controlled. The
termination resistor value can be set using an external ZQ resistor or disabled through the Extended Mode Register.
The output driver impedance can be set using the Extended Mode Register. It can either be set to ZQ / 6 (auto calibration) or
to 35, 40 or 45 Ohms.
Auto Refresh and Power Down with Self Refresh operations are supported.
An industrial standard PG-TFBGA-136 package is used which enables ultra high speed data transfer rates and a simple
upgrade path from former DDR Graphics SDRAM products.
Rev. 0.92, 2007-10
4
06122007-MW7D-3G3M