HYB18H1G321AF Datasheet, PDF (38/48 Pages) Qimonda AG – GDDR3 Graphics RAM 1-Gbit GDDR3 Graphics RAM

Internet Data Sheet
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
Symbol Parameter/Condition
I_DD6
Self Refresh Current
CKE ≤ max(V_IL), external clock off, CK and CK LOW; Address and control inputs are STABLE (HIGH); Data Bus
inputs are STABLE (HIGH).
I_DD7
Operating Bank Interleave Read Current
1. 1-CS Mode: All banks interleaving with CL = CL(min); t_RCD = t_RCDRD(min); t_RRD = t_RRD(min); I_out=0 mA; Address
and control inputs are STABLE (HIGH) during DESELECT; Data bus inputs are SWITCHING.
2: 2-CS: All banks and all ranks interleaving with CL = CL(min); t_RCD = t_RCDRD(min); t_RRD = t_RRD(min); t_{RRD_RR} =
t_{RRD_RR}(min); I_out=0 mA; Address and control inputs are STABLE (HIGH) during DESELECT; Data bus inputs are
SWITCHING.
Notes
1. 0 °C ≤ Tc ≤ 95 °C
2. Data Bus consists of DQ, DM, WDQS.
3. Definitions for IDD:
LOW is defined as VIN = 0.4 × VDDQ; HIGH is defined as V_IN = V_DDQ;
TABLE is defined as inputs are stable at a HIGH level.
SWITCHING is defined as inputs are changing between HIGH and LOW every clock cycle for address and control signals,
and inputs changing 50% of each data transfer for DQ signals.
Rev. 0.92, 2007-10
38
06122007-MW7D-3G3M