HYB18H1G321AF Datasheet, PDF (39/48 Pages) Qimonda AG – GDDR3 Graphics RAM 1-Gbit GDDR3 Graphics RAM

Internet Data Sheet
5.12
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
AC Timings for HYB18H1G321AF–10/11/14
Parameter
CAS
latency
Symbo
l
–10
TABLE 22
Timing Parameters (HYB18H1G321AF–10/11/14 )
Limit Values
Unit Note
–11
-14
min
max
min
max
min
Clock and Clock Enable
System frequency CL = 12
f_CK12
450
CL =11
f_CK11
400
CL = 9
f_CK9
—
Clock high level width
t_CH
0.45
Clock low level width
t_CL
0.45
Minimum clock half period
t_HP
0.45
Command and Address Setup and Hold Timing
1000
900
—
0.55
0.55
—
—
400
—
0.45
0.45
0.45
—
900
—
0.55
0.55
—
—
450
—
0.45
0.45
0.45
Address/Command input setup t_IS
0.24
—
0.27
—
0.35
time
Address/Command input hold time t_IH
0.24
—
0.27
—
0.35
Address/Command input pulse t_IPW
0.7
—
0.7
—
0.7
width
Mode Register Set Timing
Mode Register Set cycle time
t_MRD
6
—
6
—
6
Mode Register Set to READ timing t_MRDR 12
—
12
—
12
Row Timing
Row Cycle Time
t_RC
37
—
35
—
34
Row Active Time
t_RAS
23
—
22
—
22
ACT(a) to ACT(b) Command
period
t_RRD
9
—
8
—
7
ACT(a) to ACT(b) Command
t_{RRD_RR} —
—
1
period (different rank)
—
1
Row Precharge Time
t_RP
14
—
13
—
12
Row to Column Delay Time for
t_RCDRD 13
—
12
—
11
Reads
Row to Column Delay Time for
Writes
t_RCDWR t_RCDWR(Min) = max(t_RCDRD(Min) - (WL + 1) × t_CK;2×t_CK)
Four Active Windows within Rank t_FAW
36
—
35
—
35
Column Timing
CAS(a) to CAS(b) Command
period
t_CCD
BL/2
—
BL/2
—
BL/2
Internal write to Read Command t_WTR
7
Delay
—
6
—
6
max
—
700
—
0.55
0.55
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MHz ¹⁾
MHz ²⁾
MHz ²⁾
t_CK
3)
t_CK
3)
t_CK
3)4)
ns
ns
t_CK
3)
t_CK
5)6)
t_CK
5)
t_CK
t_CK
7)
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
8)
t_CK
9)
Rev. 0.92, 2007-10
39
06122007-MW7D-3G3M